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micron m25px64 serial flash embedded memory 64mb, dual i/o, 4kb subsector erase, serial flash memory with 75 mhz spi bus interface features ? spi bus compatible serial interface ? 75mhz (maximum) clock frequency ? 2.7v to 3.6v single supply voltage ? dual input/output commands resulting in an equivalent clock frequency of 150mhz C dual output fast read command C dual input fast program command ? continuous read of entire memory using fast read or dual output fast read command ? 64mb flash memory C uniform 4kb subsectors C uniform 64kb sectors ? additional 64b user-lockable, one-time program- mable (otp) area ? erase capability C subsector (4kb granularity) C sector (64kb granularity) C bulk erase (64mb) in 68 s typical ? write protections C software write protection: applicable to every 64kb sector (volatile lock bit) C hardware write protection: non-volatile bits bp0, bp1, bp2 define protected area size ? deep power down: 5a typical ? electronic signature C jedec standard 2b signature (7117h) C unique id code (uid) with 16b read-only space, available upon request ? more than 100,000 write cycles per sector ? more than 20 years data retention ? packages (rohs compliant) C vdfpn8 (me) 8mm x 6mm (mlp8) C vdfpn8 (md) 8mm x 6mm (mlp8) with reduced d2 dimension C so16 (mf) 300 mils width C tbga24 (zm) 6mm x 8mm ? automotive certified parts available ? this latest generation of this product line is availa- ble in the n25q device (see tn 12-13 for migration guide) micron m25px64 serial flash embedded memory features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
contents functional description ..................................................................................................................................... 5 signal descriptions ........................................................................................................................................... 8 serial peripheral interface modes ...................................................................................................................... 9 operating features ......................................................................................................................................... 11 page programming ..................................................................................................................................... 11 dual input fast program ............................................................................................................................. 11 subsector erase, sector erase, bulk erase ..................................................................................................... 11 polling during a write, program, or erase cycle ............................................................................................ 11 active power, standby power, and deep power-down .................................................................................. 11 status register ............................................................................................................................................ 12 data protection by protocol ........................................................................................................................ 12 software data protection ............................................................................................................................ 12 hardware data protection .......................................................................................................................... 13 hold condition .......................................................................................................................................... 14 memory configuration and block diagram ...................................................................................................... 15 memory map C 64mb density ......................................................................................................................... 16 command set overview ................................................................................................................................. 17 write enable .............................................................................................................................................. 19 write disable ............................................................................................................................................. 20 read identification ................................................................................................................................. 21 read status register ................................................................................................................................ 22 wip bit ...................................................................................................................................................... 23 wel bit ...................................................................................................................................................... 23 block protect bits ....................................................................................................................................... 23 top/bottom bit .......................................................................................................................................... 23 srwd bit ................................................................................................................................................... 23 write status register .............................................................................................................................. 24 read data bytes ......................................................................................................................................... 26 read data bytes at higher speed ............................................................................................................ 27 dual output fast read ............................................................................................................................ 28 read lock register ................................................................................................................................... 29 read otp ...................................................................................................................................................... 30 page program ............................................................................................................................................ 31 dual input fast program ........................................................................................................................ 32 program otp .............................................................................................................................................. 33 write to lock register ............................................................................................................................. 35 subsector erase ....................................................................................................................................... 36 sector erase .............................................................................................................................................. 37 bulk erase .................................................................................................................................................. 38 deep power-down ..................................................................................................................................... 39 release from deep power-down .............................................................................................................. 40 power-up/down and supply line decoupling ................................................................................................. 41 maximum ratings and operating conditions .................................................................................................. 43 electrical characteristics ................................................................................................................................ 44 ac characteristics .......................................................................................................................................... 45 package information ...................................................................................................................................... 51 device ordering information .......................................................................................................................... 55 revision history ............................................................................................................................................. 56 rev. b C 3/2013 ........................................................................................................................................... 56 rev. a C 6/2012 ........................................................................................................................................... 56 micron m25px64 serial flash embedded memory features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of figures figure 1: logic diagram ................................................................................................................................... 5 figure 2: pin connections: vfqfpn and so8 ................................................................................................... 6 figure 3: pin connections: so16 ...................................................................................................................... 6 figure 4: pinout: 24-ball bga, 6x8mm .............................................................................................................. 7 figure 5: bus master and memory devices on the spi bus ............................................................................... 10 figure 6: spi modes ....................................................................................................................................... 10 figure 7: hold condition activation ............................................................................................................... 14 figure 8: block diagram ................................................................................................................................ 15 figure 9: write enable command sequence .............................................................................................. 19 figure 10: write disable command sequence ............................................................................................ 20 figure 11: read identification command sequence ................................................................................ 21 figure 12: read status register command sequence .............................................................................. 22 figure 13: status register format ................................................................................................................... 22 figure 14: write status register command sequence ............................................................................. 24 figure 15: read data bytes command sequence ........................................................................................ 26 figure 16: read data bytes at higher speed command sequence ........................................................... 27 figure 17: dual output fast read command sequence ........................................................................... 28 figure 18: read lock register command sequence ................................................................................. 29 figure 19: read otp command sequence .................................................................................................... 30 figure 20: page program command sequence ........................................................................................... 31 figure 21: dual input fast program command sequence ....................................................................... 32 figure 22: program otp command sequence ............................................................................................. 33 figure 23: how to permanently lock the otp bytes ........................................................................................ 34 figure 24: write to lock register instruction sequence ........................................................................... 35 figure 25: subsector erase command sequence ...................................................................................... 36 figure 26: sector erase command sequence ............................................................................................. 37 figure 27: bulk erase command sequence ................................................................................................. 38 figure 28: deep power-down command sequence ................................................................................... 39 figure 29: release from deep power-down command sequence ............................................................. 40 figure 30: power-up timing .......................................................................................................................... 42 figure 31: ac measurement i/o waveform ..................................................................................................... 45 figure 32: serial input timing ........................................................................................................................ 48 figure 33: write protect setup and hold during wrsr when srwd=1 timing ................................................. 48 figure 34: hold timing .................................................................................................................................. 49 figure 35: output timing .............................................................................................................................. 49 figure 36: vpph timing ................................................................................................................................. 50 figure 37: vdfpn8 (mlp8, me) 6mm x 8mm ................................................................................................. 51 figure 38: vdfpn8 (mlp8, md) 6mm x 8mm with reduced d2 dimension ..................................................... 52 figure 39: so16w 300 mils body width .......................................................................................................... 53 figure 40: tbga 24-ball, 6mm x 8mm ............................................................................................................ 54 micron m25px64 serial flash embedded memory features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of tables table 1: signal names ...................................................................................................................................... 6 table 2: signal descriptions ............................................................................................................................. 8 table 3: spi modes .......................................................................................................................................... 9 table 4: software protection truth table ........................................................................................................ 13 table 5: sectors 0 to 127, protected area sizes C upper area protection ............................................................ 13 table 6: sectors 0 to 127, protected area sizes C lower area protection ............................................................ 13 table 7: sectors[127:0] ................................................................................................................................... 16 table 8: command set codes ........................................................................................................................ 18 table 9: read identification data out sequence ..................................................................................... 21 table 10: status register protection modes ..................................................................................................... 25 table 11: lock register out ............................................................................................................................ 29 table 12: lock register in .............................................................................................................................. 35 table 13: absolute maximum ratings ............................................................................................................. 43 table 14: operating conditions ...................................................................................................................... 43 table 15: data retention and endurance ........................................................................................................ 43 table 16: power up timing specifications ...................................................................................................... 44 table 17: dc current specifications ............................................................................................................... 44 table 18: dc voltage specifications ................................................................................................................ 44 table 19: ac measurement conditions ........................................................................................................... 45 table 20: capacitance .................................................................................................................................... 45 table 21: ac specifications (75mhz) .............................................................................................................. 46 table 22: part number information scheme ................................................................................................... 55 micron m25px64 serial flash embedded memory features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
functional description the m25px64 is a 64mb (8mb x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the device supports two high-performance dual input/output instructions that double the transfer bandwidth for read and program operations: ? dual output fast read instruction reads data at up to 75 mhz by using both pin dq1 and pin dq0 as outputs. ? dual input fast program instruction programs data at up to 75 mhz by using both pin dq1 and pin dq0 as inputs. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. it is organized as 128 sectors that are further divided into 16 subsectors each (2048 total subsectors). the memory can be erased a 4kb subsector at a time, a 64kb sector at a time, or as a whole. it can be write protected by software using a mix of volatile and non-volatile pro- tection features, depending on the application needs. protection granularity is 64kb sectors. the device has 64 one-time-programmable bytes (otp bytes) that can be read and pro- grammed using two dedicated instructions, read otp and program otp, respective- ly. these 64 bytes can be locked permanently using a program otp command se- quence. further features are available as additional security options. more information on these security features is available, upon completion of an nda (nondisclosure agreement), and are, therefore, not described in this datasheet. for more details of this option con- tact your nearest micron sales office. figure 1: logic diagram s# v cc hold# v ss dq1 c dq0 w#/v pp micron m25px64 serial flash embedded memory functional description pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 1: signal names signal name function direction c serial clock input dq0 serial data input (serves as output during dual output fast read operation) i/o dq1 serial data output (serves as input during dual input fast program operation) i/o s# chip select input w#/v pp write protect or enhanced program supply voltage input hold# hold input v cc supply voltage v ss ground figure 2: pin connections: vfqfpn and so8 1 2 3 4 v cc hold# 5 6 7 8 dq1 v ss s# dq0 c w#/v pp there is an exposed central pad on the underside of the vfqfpn package. this is pulled internally to v ss , and must not be connected to any other voltage or signal line on the pcb. the package mechanical section provides information on package dimensions and how to identify pin 1. figure 3: pin connections: so16 1 2 3 4 16 15 14 13 v cc hold# dnu dnu dnu dnu dnu dnu dnu dnu 5 6 7 8 12 11 10 9 dq1 v ss s# dq0 c w#/v pp note: 1. dnu = do not use. micron m25px64 serial flash embedded memory functional description pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 4: pinout: 24-ball bga, 6x8mm a b c d e 1 2 3 4 5 nc nc nc nc nc nc v cc w#/v pp hold# nc nc v ss nc dq0 nc nc c s# dq1 nc nc nc nc nc note: 1. dnu = do not use. nc = no connect. micron m25px64 serial flash embedded memory functional description pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal descriptions table 2: signal descriptions signal type description dq1 output serial data: the dq1 output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock (c). during the dual input fast program command, pin dq1 is used as an input. it is latched on the rising edge of c. dq0 input serial data: the dq0 input signal is used to transfer data serially into the device. it receives commands, addresses, and the data to be programmed. values are latched on the rising edge of the serial clock (c). during the dual output fast read command, pin dq0 is used as an output. data is shifted out on the falling edge of c. c input clock: the c input signal provides the timing of the serial interface. commands, ad- dresses, or data present at serial data input (dq0) is latched on the rising edge of the serial clock (c). data on dq1 changes after the falling edge of c. s# input chip select: when the s# input signal is high, the device is deselected and dq1 is at high impedance. unless an internal program, erase, or write status register cy- cle is in progress, the device will be in the standby power mode (not the deep power- down mode). driving s# low enables the device, placing it in the active power mode. after power-up, a falling edge on s# is required prior to the start of any com- mand. hold# input hold: the hold# signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, dq1 is high-z. dq0 and c are "dont care." to start the hold condition, the device must be selected, with s# driven low. w#/v pp input write protect/enhanced program supply voltage: the w#/v pp signal is both a con- trol input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if the w#/v pp input is kept in a low voltage range (0 v to v cc ) the pin is seen as a control input. the w# input signal is used to freeze the size of the area of memory that is protected against program or erase commands as specified by the values in bp2, bp1, and bp0 bits of the status register. v pp acts as an additional power supply if it is in the range of v pph , as defined in the ac measurement condi- tions table. avoid applying v pph to the w#/v pp pin during a bulk erase operation. v cc input device core power supply: source voltage. v ss input ground: reference for the v cc supply voltage. micron m25px64 serial flash embedded memory signal descriptions pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
serial peripheral interface modes the device can be driven by a microcontroller while its serial peripheral interface (spi) is in either of the two modes shown here. the difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock. table 3: spi modes spi modes clock polarity cpol = 0, cpha = 0 c remains at 0 for (cpol = 0, cpha = 0) cpol = 1, cpha = 1 c remains at 1 for (cpol = 1, cpha = 1) the following figure is an example of three memory devices in a simple connection to an mcu on an spi bus. because only one device is selected at a time, that one device drives dq1, while the other devices are high-z. resistors ensure the device is not selected if the bus master leaves s# high-z. the bus master might enter a state in which all input/output is high-z simultaneously, such as when the bus master is reset. therefore, the serial clock must be connected to an exter- nal pull-down resistor so that s# is pulled high while the serial clock is pulled low. this ensures that s# and the serial clock are not high simultaneously and that t shch is met. the typical resistor value of 100k , assuming that the time constant r cp (cp = parasitic capacitance of the bus line), is shorter than the time the bus master leaves the spi bus in high-z. example: cp = 50 pf, that is r cp = 5 s. the application must ensure that the bus master never leaves the spi bus high-z for a time period shorter than 5 s. w# and hold# should be driven either high or low, as appropriate. micron m25px64 serial flash embedded memory serial peripheral interface modes pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 5: bus master and memory devices on the spi bus spi bus master spi memory device sdo sdi sck c dq1 dq0 spi memory device c dq1 dq0 spi memory device c dq1 dq0 s# cs3 cs2 cs1 spi interface: (cpol, cpha) = (0, 0) or (1, 1) w# hold# s# w# hold# s# w# hold# r r r v cc v cc v cc v cc v ss v ss v ss v ss r figure 6: spi modes c c dq0 dq1 cpha 0 1 cpol 0 1 msb msb micron m25px64 serial flash embedded memory serial peripheral interface modes pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
operating features page programming to program one data byte, two commands are required: write enable, which is one byte, and a page program sequence, which is four bytes plus data. this is followed by the internal program cycle of duration t pp . to spread this overhead, the page pro- gram command allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided they lie in consecutive addresses on the same page of memory. to optimize timings, it is recommended to use the page program command to program all consecutive targeted bytes in a single sequence than to use several page program sequences with each containing only a few bytes. dual input fast program the dual input fast program command makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0). for opti- mized timings, it is recommended to use the dual input fast program command to program all consecutive targeted bytes in a single sequence than to use several dual input fast program sequences each containing only a few bytes. subsector erase, sector erase, bulk erase the page program command allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be ach- ieved a subsector at a time using the subsector erase command, a sector at a time using the sector erase command, or throughout the entire memory using the bulk erase command. this starts an internal erase cycle of duration t sse , t se or t be . the erase command must be preceded by a write enable command. polling during a write, program, or erase cycle an improvement in the time to complete the following commands can be achieved by not waiting for the worst case delay (t w , t pp , t sse , t se , or t be ). ? write status register ? program otp ? program ? dual input fast program ? erase (subsector erase, sector erase, bulk erase) the write in progress (wip) bit is provided in the status register so that the application program can monitor this bit in the status register, polling it to establish when the pre- vious write cycle, program cycle, or erase cycle is complete. active power, standby power, and deep power-down when chip select (s#) is low, the device is selected, and in the active power mode. when s# is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device con- sumption drops to i cc1 . micron m25px64 serial flash embedded memory operating features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
the deep power-down mode is entered when the deep power-down command is executed. the device consumption drops further to i cc2 . the device remains in this mode until the release from deep power-down command is executed. while in the deep power-down mode, the device ignores all write, program, and erase commands. this provides an extra software protection mechanism when the device is not in active use, by protecting the device from inadvertent write, program, or erase operations. for further information, see deep power-down (page 39). status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific commands. for a detailed description of the status register bits, see read status register (page 22). data protection by protocol non-volatile memory is used in environments that can include excessive noise. the fol- lowing capabilities help protect data in these noisy environments. power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. program, erase, and write status register commands are checked before they are accepted for execution to ensure they consist of a number of clock pulses that is a multiple of eight. all commands that modify data must be preceded by a write enable command to set the write enable latch (wel) bit. in addition to the low power consumption feature, the deep power-down mode of- fers extra software protection since all write, program, and erase commands are ignored when the device is in this mode. software data protection memory can be configured as read-only using the top/bottom bit and the block protect bits (bp2, bp1, bp0) as shown in the protected area sizes table. memory sectors can be protected by specific lock registers assigned to each 64kb sec- tor. these lock registers can be read and written using the read lock register and write to lock register commands. in each lock register the following two bits con- trol the protection of each sector: ? write lock bit: this bit determines whether the contents of the sector can be modified using the write, program, and erase commands. when the bit is set to 1, the sector is write protected, and any operations that attempt to change the data in the sector will fail. when the bit is reset to 0, the sector is not write protected by the lock register, and may be modified. ? lock down bit: this bit provides a mechanism for protecting software data from sim- ple hacking and malicious attack. when the bit is set to '1, further modification to the write lock bit and lock down bit cannot be performed. a power-up, is required before changes to these bits can be made. when the bit is reset to 0, the write lock bit and lock down bit can be changed. the software protection truth table shows the lock down bit and write lock bit settings and the sector protection status. micron m25px64 serial flash embedded memory operating features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 4: software protection truth table sector lock register bits lock down write lock protection status 0 0 sector unprotected from program / erase / write operations; protection status reversible 0 1 sector protected from program / erase / write operations; protection status reversible 1 0 sector unprotected from program / erase / write operations; protection status cannot be changed except by a power-up. 1 1 sector protected from program / erase / write operations; protection status cannot be changed except by a power-up. hardware data protection hardware data protection is implemented using the write protect signal applied on the w#/v pp pin. this freezes the status register in a read-only mode, protecting the block protect (bp) bits and the status register write disable bit (srwd). the device is ready to accept a bulk erase command only if all block protect bits are 0. table 5: sectors 0 to 127, protected area sizes C upper area protection status register content memory content top/bottom bit bp2 bp1 bp0 protected area unprotected area 0 0 0 0 none all sectors 1 0 0 0 1 upper 64th (sectors 126 to 127) lower 63/64ths (sectors 0 to 125) 0 0 1 0 upper 32nd (sectors 124 to 127) lower 31/32nds (sectors 0 to 123) 0 0 1 1 upper 16th (sectors 120 to 127) lower 15/16ths (sectors 0 to119) 0 1 0 0 upper 8th (sectors 112 to 127) lower 7/8ths (sectors 0 to 111) 0 1 0 1 upper 4th (sectors 96 to 127) lower 3/4ths (sectors 0 to 95) 0 1 1 0 upper half (sectors 64 to 127) lower half (sectors 0 to 63) 0 1 1 1 all sectors none note: 1. the device is ready to accept a bulk erase command only if all block protect bits are 0. table 6: sectors 0 to 127, protected area sizes C lower area protection status register content memory content top/bottom bit bp2 bp1 bp0 protected area unprotected area 1 0 0 0 none all sectors 1 1 0 0 1 lower 64th (sectors 0 to 1) upper (sectors 2 to 127) 1 0 1 0 lower 32nd (sectors 0 to 3) upper (sectors 4 to 127) 1 0 1 1 lower 16th (sectors 0 to 7) upper (sectors 8 to 127) 1 1 0 0 lower 8th (sectors 0 to 15) upper (sectors 16 to 127) 1 1 0 1 lower 4th (sectors 0 to 31) upper (sectors 32 to 127) 1 1 1 0 lower half (sectors 0 to 63) upper (sectors 64 to 127) micron m25px64 serial flash embedded memory operating features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 6: sectors 0 to 127, protected area sizes C lower area protection (continued) status register content memory content top/bottom bit bp2 bp1 bp0 protected area unprotected area 1 1 1 1 none all sectors note: 1. the device is ready to accept a bulk erase command only if all block protect bits are 0. hold condition the hold# signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program, or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with s# low. the hold condi- tion starts on the falling edge of the hold# signal, if this coincides with serial clock (c) being low. the hold condition ends on the rising edge of the hold# signal, if this co- incides with c being low. if the falling edge does not coincide with c being low, the hold condition starts after c next goes low. similarly, if the rising edge does not coin- cide with c being low, the hold condition ends after c next goes low. during the hold condition, dq1 is high impedance while dq0 and c are dont care. typically, the device remains selected with s# driven low for the duration of the hold condition. this ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. if s# goes high while the device is in the hold condition, the internal logic of the device is reset. to restart communication with the device, it is necessary to drive hold# high, and then to drive s# low. this prevents the device from going back to the hold condition. figure 7: hold condition activation hold# c hold condition (standard use) hold condition (nonstandard use) micron m25px64 serial flash embedded memory operating features pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
memory configuration and block diagram each page of memory can be individually programmed; bits are programmed from 1 to 0. the device is subsector, sector, or bulk-erasable, but not page-erasable; bits are erased from 0 to 1.. the memory is configured as follows: test ? 8,388,608 bytes (8 bits each) ? 2,048 subsectors (4kb each) ? 128 sectors (64kb each) ? 32,768 pages (256 bytes each) ? 64 otp bytes located outside the main memory array figure 8: block diagram hold# s# w#/v pp control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c dq0 dq1 status register 00000h 7fffffh 000ffh micron m25px64 serial flash embedded memory memory configuration and block diagram pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
memory map C 64mb density table 7: sectors[127:0] sector subsector address range start end 127 2047 007f f000h 007f ffffh ? ? ? 2032 007f 0000h 007f 0fffh ? ? ? ? 63 1023 003f f000h 003f ffffh ? ? ? 1008 003f 0000h 003f 0fffh ? ? ? ? 0 15 0000 f000h 0000 ffffh ? ? ? 0 0000 0000h 0000 0fffh micron m25px64 serial flash embedded memory memory map C 64mb density pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
command set overview all commands, addresses, and data are shifted in and out of the device, most significant bit first. serial data inputs dq0 and dq1 are sampled on the first rising edge of serial clock (c) after chip select (s#) is driven low. then, the one-byte command code must be shifted in to the device, most significant bit first, on dq0 and dq1, each bit being latched on the rising edges of c. every command sequence starts with a one-byte command code. depending on the command, this command code might be followed by address or data bytes, by address and data bytes, or by neither address or data bytes. for the following commands, the shifted-in command sequence is followed by a data-out sequence. s# can be driven high after any bit of the data-out sequence is being shifted out. ? read data bytes (read) ? read data bytes at higher speed ? dual output fast read ? read otp ? read lock registers ? read status register ? read identification ? release from deep power-down for the following commands, s# must be driven high exactly at a byte boundary. that is, after an exact multiple of eight clock pulses following s# being driven low, s# must be driven high. otherwise, the command is rejected and not executed. ? page program ? program otp ? dual input fast program ? subsector erase ? sector erase ? bulk erase ? write status register ? write to lock register ? write enable ? write disable ? deep power-down all attempts to access the memory array are ignored during a write status register command cycle, a program command cycle, or an erase command cycle. in addi- tion, the internal cycle for each of these commands continues unaffected. micron m25px64 serial flash embedded memory command set overview pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 8: command set codes command name one-byte command code bytes address dummy data write enable 0000 0110 06h 0 0 0 write disable 0000 0100 04h 0 0 0 read identification 1001 1111 9fh 0 0 1 to 20 1001 1110 9eh 1 to 20 read status register 0000 0101 05h 0 0 1 to write status register 0000 0001 01h 0 0 1 write to lock register 1110 0101 e5h 3 0 1 read lock register 1110 1000 e8h 3 0 1 read data bytes 0000 0011 03h 3 0 1 to read data bytes at higher speed 0000 1011 0bh 3 1 1 to dual output fast read 0011 1011 3bh 3 1 1 to read otp (read 64 bytes of otp area) 0100 1011 4bh 3 1 1 to 65 program otp (program 64 bytes of otp area) 0100 0010 42h 3 0 1 to 65 page program 0000 0010 02h 3 0 1 to 256 dual input fast program 1010 0010 a2h 3 0 1 to 256 subsector erase 0010 0000 20h 3 0 0 sector erase 1101 1000 d8h 3 0 0 bulk erase 1100 0111 c7h 0 0 0 deep power-down 1011 1001 b9h 0 0 0 release from deep power-down 1010 1011 abh 0 0 0 micron m25px64 serial flash embedded memory command set overview pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
write enable the write enable command sets the write enable latch (wel) bit. the wel bit must be set before execution of every program, erase, and write com- mand. the write enable command is entered by driving chip select (s#) low, sending the command code, and then driving s# high. figure 9: write enable command sequence dont care dq[0] 0 1 2 4 5 3 7 6 c high-z dq1 msb lsb 0 0 0 0 0 0 1 1 command bits s# micron m25px64 serial flash embedded memory write enable pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
write disable the write disable command resets the write enable latch (wel) bit. the write disable command is entered by driving chip select (s#) low, sending the command code, and then driving s# high. the wel bit is reset under the following conditions: ? power-up ? completion of any erase operation ? completion of any program operation ? completion of any write register operation ? completion of write disable operation figure 10: write disable command sequence dont care dq[0] 0 1 2 4 5 3 7 6 c high-z dq1 msb lsb 0 0 0 0 0 0 0 1 command bits s# micron m25px64 serial flash embedded memory write disable pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read identification the read identification command reads the following device identification data: ? manufacturer identification (1 byte): this is assigned by jedec. ? device identification (2 bytes): this is assigned by device manufacturer; the first byte indicates memory type and the second byte indicates device memory capacity. ? a unique id code (uid) (17 bytes,16 available upon customer request): the first byte contains length of data to follow; the remaining 16 bytes contain optional customized factory data (cfd) content. table 9: read identification data out sequence manufacturer identification device identification uid memory type memory capacity cfd length cfd content 20h 71h 17h 10h 16 bytes note: 1. the cfd bytes are read-only and can be programmed with customer data upon demand. if customers do not make requests, the devices are shipped with all the cfd bytes pro- grammed to zero. a read identification command is not decoded while an erase or program cy- cle is in progress and has no effect on a cycle in progress. the read identification command must not be issued while the device is in deep power-down mode. the device is first selected by driving s# low. then the 8-bit command code is shifted in and content is shifted out on dq1 as follows: the 24-bit device identification that is stored in the memory, the 8-bit cfd length, followed by 16 bytes of cfd content. each bit is shifted out during the falling edge of serial clock (c). the read identification command is terminated by driving s# high at any time during data output. when s# is driven high, the device is put in the standby power mode and waits to be selected so that it can receive, decode, and execute commands. figure 11: read identification command sequence uid device identification manufacturer identification high-z dq1 msb msb d out d out d out d out lsb lsb 7 8 15 16 32 31 0 c msb dq0 lsb command msb d out d out lsb dont care micron m25px64 serial flash embedded memory read identification pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read status register the read status register command allows the status register to be read. the status register may be read at any time, even while a program, erase, or write status register cycle is in progress. when one of these cycles is in progress, it is recommen- ded to check the write in progress (wip) bit before sending a new command to the de- vice. it is also possible to read the status register continuously. figure 12: read status register command sequence high-z dq1 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command msb d out d out d out d out d out lsb d out d out d out d out dont care figure 13: status register format b7 srwd 0 tb bp2 bp1 bp0 wel wip b0 status register write protect block protect bits top/bottom bit write enable latch bit write in progress bit micron m25px64 serial flash embedded memory read status register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register cycle, a program cycle, or an erase cycle. when the wip bit is set to 1, a cycle is in progress; when the wip bit is set to 0, a cycle is not in progress. wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel bit is set to 1, the internal write enable latch is set; when the wel bit is set to 0, the internal write enable latch is reset and no write status register, pro- gram, or erase command is accepted. block protect bits the block protect bits are non-volatile. they define the size of the area to be software protected against program and erase commands. the block protect bits are written with the write status register command. when one or more of the block protect bits is set to 1, the relevant memory area, as de- fined in the protected area sizes table, becomes protected against page program and sector erase commands. the block protect bits can be written provided that the hardware protected mode has not been set. the bulk erase command is execu- ted only if all block protect bits are 0. top/bottom bit the top/bottom (tb) bit is non-volatile. it can be set and reset with the write status register command provided that the write enable command has been issued. the tb bit is used in conjunction with the block protect bits to determine if the protected area defined by the block protect bits starts from the top or the bottom of the memory array: ? when tb is reset to 0 (default value), the area protected by the block protect bits starts from the top of the memory array ? when tb is set to 1, the area protected by the block protect bits starts from the bot- tom of the memory array the tb bit cannot be written when the status register write disable (srwd) bit is set to 1 and the w# pin is driven low. for further information, see on page srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w#/v pp ) signal. when the srwd bit is set to 1 and w#/v pp is driven low, the device is put in the hardware protected mode. in the hardware protected mode, the non-volatile bits of the status register (srwd, and the block protect bits) become read- only bits and the write status register command is no longer accepted for execu- tion. micron m25px64 serial flash embedded memory read status register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
write status register the write status register command allows new values to be written to the status register. before the write status register command can be accepted, a write en- able command must have been executed previously. after the write enable com- mand has been decoded and executed, the device sets the write enable latch (wel) bit. the write status register command is entered by driving chip select (s#) low, followed by the command code and the data byte on serial data input (dq0). the write status register command has no effect on b6, b1 and b0 of the status regis- ter. the status register b6 is always read as 0. s# must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register command is not executed. figure 14: write status register command sequence 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command msb lsb d in d in d in d in d in d in d in d in d in as soon as s# is driven high, the self-timed write status register cycle is initi- ated; its duration is t w . while the write status register cycle is in progress, the sta- tus register may still be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed write status register cycle, and is 0 when the cycle is completed. also, when the cycle is completed, the wel bit is reset. the write status register command allows the user to change the values of the block protect bits (bp2, bp1, bp0). setting these bit values defines the size of the area that is to be treated as read-only, as defined in the protected area sizes table. the write status register command also allows the user to set and reset the status register write disable (srwd) bit in accordance with the write protect (w#/v pp ) signal. the srwd bit and the w#/v pp signal allow the device to be put in the hardware pro- teced (hpm) mode. the write status register command is not executed once the hpm is entered. the options for enabling the status register protection modes are summarized here. micron m25px64 serial flash embedded memory write status register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 10: status register protection modes w#/v pp signal srwd bit protection mode (pm) status register write protection memory content notes protected area unprotected area 1 0 software protected mode (spm) software protection commands not accepted commands accepted 1, 2, 3 0 0 1 1 0 1 hardware protected mode (hpm) hardware protection commands not accepted commands accepted 3, 4, 5, notes: 1. software protection: status register is writable (srwd, bp2, bp1, and bp0 bit values can be changed) if the write enable command has set the wel bit. 2. page program, sector erase, and bulk erase commands are not accepted. 3. page program and sector erase commands can be accepted. 4. hardware protection: status register is not writable (srwd, bp2, bp1, and bp0 bit values cannot be changed). 5. page program, sector erase, and bulk erase commands are not accepted. when the srwd bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the wel bit has been set previously by a write enable command, regardless of whether the w#/v pp signal is driven high or low. when the status register srwd bit is set to 1, two cases need to be considered depend- ing on the state of the w#/v pp signal: ? if the w#/v pp signal is driven high, it is possible to write to the status register provi- ded that the wel bit has been set previously by a write enable command. ? if the w#/v pp signal is driven low, it is not possible to write to the status register even if the wel bit has been set previously by a write enable command. therefore, at- tempts to write to the status register are rejected, and are not accepted for execution. the result is that all the data bytes in the memory area that have been put in spm by the status register block protect bits (bp2, bp1, bp0) are also hardware protected against data modification. regardless of the order of the two events, the hpm can be entered in either of the fol- lowing ways: ? setting the status register srwd bit after driving the w#/v pp signal low ? driving the w#/v pp signal low after setting the status register srwd bit. the only way to exit the hpm is to pull the w#/v pp signal high. if the w#/v pp signal is permanently tied high, the hpm can never be activated. in this case, only the spm is available, using the status register block protect bits (bp2, bp1, bp0). micron m25px64 serial flash embedded memory write status register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read data bytes the device is first selected by driving chip select (s#) low. the command code for read data bytes is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents at that address is shifted out on serial data output (dq1), each bit being shifted out at a maximum fre- quency f r during the falling edge of c. the first byte addressed can be at any location. the address is automatically incremen- ted to the next higher address after each byte of data is shifted out. therefore, the entire memory can be read with a single read data bytes command. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes command is terminated by driving s# high. s# can be driven high at any time during data output. any read data bytes command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 15: read data bytes command sequence dont care msb dq[0] lsb command a[max] a[min] 7 8 c x 0 c high-z dq1 msb d out d out d out d out d out lsb d out d out d out d out note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory read data bytes pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read data bytes at higher speed the device is first selected by driving chip select (s#) low. the command code for the read data bytes at higher speed command is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents at that address are shifted out on serial data output (dq1) at a maximum frequency f c , during the falling edge of c. the first byte addressed can be at any location. the address is automatically incremen- ted to the next higher address after each byte of data is shifted out. therefore, the entire memory can be read with a single read data bytes at higher speed command. when the highest address is reached, the address counter rolls over to 000000h, allow- ing the read sequence to be continued indefinitely. the read data bytes at higher speed command is terminated by driving s# high. s# can be driven high at any time during data output. any read data bytes at higher speed command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 16: read data bytes at higher speed command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] msb d out d out d out d out d out lsb d out d out d out d out dummy cycles dq1 high-z dont care note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory read data bytes at higher speed pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dual output fast read the dual output fast read command is similar to the read data bytes at higher speed command, except that data is shifted out on two pins (dq0 and dq1) instead of one. outputting the data on two pins doubles the data transfer bandwidth compared to the read data bytes at higher speed command. the device is first selected by driving chip select s# low. the command code for the dual output fast read command is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents at that address are shifted out on dq0 and dq1 at a maximum frequency f c , during the falling edge of c. figure 17: dual output fast read command sequence 7 8 c x 0 c msb dq0 lsb command d out lsb dq1 d out a[max] high-z a[min] d out msb d out d out d out d out d out d out d out dummy cycles note: 1. cx = 7 + (a[max] + 1). the first byte addressed can be at any location. the address is automatically incremen- ted to the next higher address after each byte of data is shifted out on dq0 and dq1. therefore, the entire memory can be read with a single dual output fast read command. when the highest address is reached, the address counter rolls over to 00 0000h so that the read sequence can be continued indefinitely. micron m25px64 serial flash embedded memory dual output fast read pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read lock register the device is first selected by driving chip select (s#) low. the command code for the read lock register command is followed by a 3-byte address (a23-a0) pointing to any location inside the concerned sector. each address bit is latched-in during the ris- ing edge of serial clock (c). then the value of the lock register is shifted out on serial data output (dq1), each bit being shifted out at a maximum frequency f c during the falling edge of c. the read lock register command is terminated by driving s# high at any time during data output. figure 18: read lock register command sequence msb dq[0] lsb command a[max] a[min] 7 8 c x 0 c high-z dq1 msb d out d out d out d out d out lsb d out d out d out d out dont care note: 1. cx = 7 + (a[max] + 1). any read lock register command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. values of b1 and b0 after power-up are defined in power-up/down and supply line de- coupling (page 41). table 11: lock register out bit bit name value function b7-b2 reserved b1 sector lock down 1 the write lock and lock-down bits cannot be changed. once a value of 1 is writ- ten to the lock-down bit, it cannot be cleared to a value of 0 except by a power- up. 0 the write lock and lock-down bits can be changed by writing new values to them. b0 sector write lock 1 write, program, and erase operations in this sector will not be executed. the memory contents will not be changed. 0 write, program, or erase operations in this sector are executed and will modify the sector contents. micron m25px64 serial flash embedded memory read lock register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read otp the device is first selected by driving chip select (s#) low. the command code for the read otp (one-time programmable) command is followed by a 3-byte address (a23- a0) and a dummy byte. each bit is latched in on the rising edge of serial clock (c). then the memory contents at that address are shifted out on serial data output (dq1). each bit is shifted out at the maximum frequency f c max on the falling edge of c. the address is automatically incremented to the next higher address after each byte of data is shifted out. there is no rollover mechanism with the read otp command. this means that the read otp command must be sent with a maximum of 65 bytes to read because once the 65 th byte has been read, the same 65 th byte continues to be read on the dq1 pin. the read otp command is terminated by driving s# high. s# can be driven high at any time during data output. any read otp command issued while an erase, pro- gram, or write cycle is in progress is rejected without having any effect on the cycle that is in progress. figure 19: read otp command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] msb d out d out d out d out d out lsb d out d out d out d out dummy cycles dq1 high-z dont care note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory read otp pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
page program the page program command allows bytes in the memory to be programmed, which means the bits are changed from 1 to 0. before a page program command can be ac- cepted a write enable command must be executed. after the write enable com- mand has been decoded, the device sets the write enable latch (wel) bit. the page program command is entered by driving chip select (s#) low, followed by the command code, three address bytes, and at least one data byte on serial data input (dq0). if the eight least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (a7-a0) are all zero. s# must be driven low for the entire duration of the sequence. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program command to program all consecutive targeted bytes in a single sequence rather than to use several page program sequences, each containing only a few bytes. s# must be driven high after the eighth bit of the last data byte has been latched in. otherwise the page program command is not executed. as soon as s# is driven high, the self-timed page program cycle is initiated; the cy- cles's duration is t pp . while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed page program cycle, and 0 when the cycle is completed. at some un- specified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program command is not executed if it applies to a page protected by the block protect bits bp2, bp1, and bp0. figure 20: page program command sequence 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory page program pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dual input fast program the dual input fast program command is similar to the page program com- mand, except that data is entered on two pins (dq0 and dq1) instead of one, doubling the data transfer bandwidth. the dual input fast program command is entered by driving chip select s# low, followed by the command code, three address bytes, and at least one data byte on serial data input (dq0). if the eight least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page is programmed from the start address of the same page; that is, from the address whose eight least significant bits (a7-a0) are all zero. s# must be driven low for the entire duration of the sequence. if more than 256 bytes are sent to the device, previously latched data is discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effect on other bytes in the same page. for optimized timings, it is recommended to use the dual input fast program command to program all consecutive targeted bytes in a single sequence than to use several dual input fast program sequences, each containing only a few bytes. s# must be driven high after the eighth bit of the last data byte has been latched in. otherwise the dual input fast program command is not executed. as soon as s# is driven high, the self-timed page program cycle is initiated; the cy- cle's duration is t pp . while the dual input fast program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed page program cycle, and 0 when the cycle is com- pleted. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a dual input fast program command is not executed if it applies to a page protec- ted by the block protect bits bp2, bp1, and bp0. figure 21: dual input fast program command sequence 7 8 c x 0 c msb dq0 lsb command d in lsb dq1 d in a[max] high-z a[min] d in msb d in d in d in d in d in d in d in note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory dual input fast program pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program otp the program otp command allows a maximum of 64 bytes in the otp memory area to be programmed, which means the bits are changed from 1 to 0. before a program otp command can be accepted, a write enable command must have been executed previously. after the write enable command has been decoded, the device sets the write enable latch (wel) bit. the program otp command is entered by driving chip select (s#) low, followed by the command opcode, three address bytes, and at least one data byte on serial data in- put (dq0). s# must be driven high after the eighth bit of the last data byte has been latched in. otherwise the program otp command is not executed. there is no rollover mechanism with the program otp command. this means that the program otp command must be sent with a maximum of 65 bytes to program. when all 65 bytes have been latched in, any following byte will be discarded. as soon as s# is driven high, the self-timed page program cycle is initiated; the cy- cle's duration is t pp . while the program otp cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed program otp cycle, and 0 when when the cycle is completed. at some unspecified time before the cycle is complete, the wel bit is reset. figure 22: program otp command sequence 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in note: 1. cx = 7 + (a[max] + 1). the otp control byte is byte 64. bit 0 of this otp control byte is used to permanently lock the otp memory array. ? when bit 0 of the otp control byte = 1, the 64 bytes of the otp memory array can be programmed. ? when bit 0 of the otp control byte = 0, the 64 bytes of the otp memory array are read-only and cannot be programmed anymore. once a bit of the otp memory has been programmed to 0, it can no longer be set to 1. therefore, as soon as bit 0 of the control byte is set to 0, the 64 bytes of the otp memory array is set permanently as read-only. any program otp command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. micron m25px64 serial flash embedded memory program otp pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 23: how to permanently lock the otp bytes byte 0 byte 1 byte 2 byte 64 byte 63 x x x x x x x bit 0 otp control byte 64 data bytes bit 1 to bit 7 are not programmable when bit 0 = 0 the 64 otp bytes become read only micron m25px64 serial flash embedded memory program otp pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
write to lock register the write to lock register instruction allows the lock register bits to be changed. before the write to lock register instruction can be accepted, a write enable instruction must have been executed previously. after the write enable instruction has been decoded, the device sets the write enable latch (wel) bit. the write to lock register instruction is entered by driving chip select (s#) low, followed by the instruction code, three address bytes, and one data byte on serial data input (dq0). the address bytes must point to any address in the targeted sector. s# must be driven high after the eighth bit of the data byte has been latched in. otherwise the write to lock register instruction is not executed. lock register bits are volatile, and therefore do not require time to be written. when the write to lock register instruction has been successfully executed, the wel bit is reset after a delay time of less than t shsl minimum value. any write to lock register instruction issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 24: write to lock register instruction sequence 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in note: 1. cx = 7 + (a[max] + 1). table 12: lock register in sector bit value all sectors b7Cb2 0 all sectors b1 sector lock-down bit value all sectors b0 sector write lock bit value note: values of b1 and b0 after power-up are defined in power-up/down and supply line decoupling (page 41). for the sector lock down and sector write lock values, see the lock register out table in read lock register (page 29). micron m25px64 serial flash embedded memory write to lock register pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
subsector erase the subsector erase command sets to 1 (ffh) all bits inside the chosen subsector. before the subsector erase command can be accepted, a write enable com- mand must have been executed previously. after the write enable command has been decoded, the device sets the write enable latch (wel) bit. the subsector erase command is entered by driving chip select (s#) low, followed by the command code, and three address bytes on serial data input (dq0). any address inside the subsector is a valid address for the subsector erase command. s# must be driven low for the entire duration of the sequence. s# must be driven high after the eighth bit of the last address byte has been latched in. otherwise the subsector erase command is not executed. as soon as s# is driven high, the self-timed subsector erase cycle is initiated; the cycle's duration is t sse . while the subsector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed subsector erase cycle, and is 0 when the cycle is completed. at some unspecified time before the cycle is complete, the wel bit is reset. a subsector erase command issued to a sector that is hardware or software protec- ted is not executed. any subsector erase command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 25: subsector erase command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory subsector erase pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
sector erase the sector erase command sets to 1 (ffh) all bits inside the chosen sector. before the sector erase command can be accepted, a write enable command must have been executed previously. after the write enable command has been decoded, the device sets the write enable latch (wel) bit. the sector erase command is entered by driving chip select (s#) low, followed by the command code, and three address bytes on serial data input (dq0). any address in- side the sector is a valid address for the sector erase command. s# must be driven low for the entire duration of the sequence. s# must be driven high after the eighth bit of the last address byte has been latched in. otherwise the sector erase command is not executed. as soon as s# is driven high, the self-timed sector erase cycle is initiated; the cycle's duration is t se . while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed sector erase cycle, and is 0 when the cycle is completed. at some unspecified time before the cycle is completed, the wel bit is reset. a sector erase command is not executed if it applies to a sector that is hardware or software protected. figure 26: sector erase command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] note: 1. cx = 7 + (a[max] + 1). micron m25px64 serial flash embedded memory sector erase pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bulk erase the bulk erase command sets all bits to 1 (ffh). before the bulk erase command can be accepted, a write enable command must have been executed previously. af- ter the write enable command has been decoded, the device sets the write enable latch (wel) bit. the bulk erase command is entered by driving chip select (s#) low, followed by the command code on serial data input (dq0). s# must be driven low for the entire dura- tion of the sequence. s# must be driven high after the eighth bit of the command code has been latched in. otherwise the bulk erase command is not executed. as soon as s# is driven high, the self-timed bulk erase cycle is initiated; the cycle's duration is t be . while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed bulk erase cycle, and is 0 when the cycle is completed. at some unspecified time before the cycle is completed, the wel bit is reset. the bulk erase command is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase command is ignored if one or more sectors are protected. figure 27: bulk erase command sequence 7 0 c msb dq0 lsb command micron m25px64 serial flash embedded memory bulk erase pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
deep power-down executing the deep power-down command is the only way to put the device in the lowest power consumption mode, the deep power-down mode. the deep power- down command can also be used as a software protection mechanism while the de- vice is not in active use because in the deep power-down mode the device ignores all write, program, and erase commands. driving chip select (s#) high deselects the device, and puts it in the standby power mode if there is no internal cycle currently in progress. once in standby power mode, the deep power-down mode can be entered by executing the deep power- down command, subsequently reducing the standby current from i cc1 to i cc2 . to take the device out of deep power-down mode, the release from deep pow- er-down command must be issued. other commands must not be issued while the device is in deep power-down mode. the deep power-down mode stops auto- matically at power-down. the device always powers up in standby power mode. the deep power-down command is entered by driving s# low, followed by the command code on serial data input (dq0). s# must be driven low for the entire dura- tion of the sequence. s# must be driven high after the eighth bit of the command code has been latched in. otherwise the deep power-down command is not executed. as soon as s# is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down command issued while an erase, program, or write cy- cle is in progress is rejected without any effect on the cycle that is in progress. figure 28: deep power-down command sequence 7 0 c msb dq0 lsb t dp command dont care deep power-down mode standby mode micron m25px64 serial flash embedded memory deep power-down pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
release from deep power-down once the device has entered deep power-down mode, all commands are ignored ex- cept release from deep power-down. executing this command takes the device out of the deep power-down mode. the release from deep power-down command is entered by driving chip select (s#) low, followed by the command code on serial data input (dq0). s# must be driven low for the entire duration of the sequence. the release from deep power-down command is terminated by driving s# high. sending additional clock cycles on serial clock c while s# is driven low causes the command to be rejected and not executed. after s# has been driven high, followed by a delay, t rdp , the device is put in the stand- by mode. s# must remain high at least until this period is over. the device waits to be selected so that it can receive, decode, and execute commands. any release from deep power-down command issued while an erase, pro- gram, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 29: release from deep power-down command sequence high-z dq1 7 0 c msb dq0 lsb t rdp command dont care deep power-down mode standby mode micron m25px64 serial flash embedded memory release from deep power-down pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
power-up/down and supply line decoupling at power-up and power-down, the device must not be selected; that is, chip select (s#) must follow the voltage applied on v cc until v cc reaches the correct value: ? v cc,min at power-up, and then for a further delay of t vsl ? v ss at power-down a safe configuration is provided in the spi modes section. to avoid data corruption and inadvertent write operations during power-up, a power- on-reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold voltage, v wi C all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores the following instruc- tions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold: ? write enable ? page program ? dual input fast program ? program otp ? subsector erase ? sector erase ? bulk erase ? write status register ? write to lock register however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc.min . no write status register, program, or erase instruction should be sent until: ? t puw after v cc has passed the v wi threshold ? t vsl after v cc has passed the v cc,min level if the time, t vsl, has elapsed, after v cc rises above v cc,min , the device can be selected for read instructions even if the t puw delay has not yet fully elapsed. v pph must be applied only when v cc is stable and in the v cc,min to v cc,max voltage range. micron m25px64 serial flash embedded memory power-up/down and supply line decoupling pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 30: power-up timing v cc v cc,min v wi reset state of the device chip selection not allowed program, erase, and write commands are rejected by the device t vsl t puw time read access allowed device fully accessible v cc,max after power-up, the device is in the following state: ? standby power mode (not the deep power-down mode) ? write enable latch (wel) bit is reset ? write in progress (wip) bit is reset ? write lock bit = 0 ? lock down bit = 0 normal precautions must be taken for supply line decoupling to stabilize the v cc sup- ply. each device in a system should have the v cc line decoupled by a suitable capacitor close to the package pins; generally, this capacitor is of the order of 100 nf. at power-down, when v cc drops from the operating voltage to below the por threshold voltage v wi , all operations are disabled and the device does not respond to any instruc- tion. note: if power-down occurs while a write, program, or erase cycle is in progress, some data corruption may result. micron m25px64 serial flash embedded memory power-up/down and supply line decoupling pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
maximum ratings and operating conditions caution: stressing the device beyond the absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only and operation of the device be- yond any specification or condition in the operating sections of this datasheet is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 13: absolute maximum ratings symbol parameter min max units notes t stg storage temperature C65 150 c t lead lead temperature during soldering see note c 1 v io input and output voltage (with respect to ground) C0.6 v cc +0.6 v v cc supply voltage C0.6 4.0 v v pp fast program / erase voltage C0.2 10.0 v 2 v esd electrostatic discharge voltage (human body model) C2000 2000 v 3 notes: 1. the t lead signal is compliant with jedec std j-std-020c (for small body, sn-pb or pb as- sembly), the micron rohs compliant 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. avoid applying v pph to the w#/vpp pin during the bulk erase operation. 3. the v esd signal: jedec std jesd22-a114a (c1 = 100 pf, r1 = 1500 , r2 = 500 ). table 14: operating conditions symbol parameter min max unit v cc supply voltage 2.7 3.6 v v pph supply voltage on v pp pin 8.5 9.5 v t a ambient operating temperature (device grade 6) C40 85 c t a ambient operating temperature (device grade 3) C40 125 c table 15: data retention and endurance parameter condition min max unit program and erase cycles grade 3; autograde 6; grade 6 100,000 C cycles per sector data retention at 55c 20 C years micron m25px64 serial flash embedded memory maximum ratings and operating conditions pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
electrical characteristics table 16: power up timing specifications symbol parameter min max units t vsl v cc [min] to s# low 30 C s t puw time delay to write command 1 10 ms v wi write inhibit voltage 1.5 2.5 v table 17: dc current specifications symbol parameter test condition min max units notes i li input leakage current C C 2 a i lo output leakage current C C 2 a i cc1 standby current s# = v cc , v in = v ss or v cc C 50/100 a 1 i cc2 deep power-down current s# = v cc , v in = v ss or v cc C 10/100 a i cc3 operating current (read) c = 0.1v cc / 0.9v cc at 75mhz, dq1 = open C 12 ma c = 0.1v cc / 0.9v cc at 33mhz, dq1 = open C 4 ma operating current (dual output fast read) c = 0.1v cc / 0.9v cc at 75mhz, dq1 = open C 15 ma i cc4 operating current (page program) s# = v cc C 15 ma operating current (dual input fast program) s# = v cc C 15 ma i cc5 operating current (write status register) s# = v cc C 15 ma i cc6 operating current (sector erase) s# = v cc C 15 ma i cc7 operating current (bulk erase) s# = v cc C 15 ma note: 1. all specifications apply to both device grade 6 and device grade 3, except for the follow- ing standby and deep power-down current differences: device grade 6, i cc1 = 50a and i cc2 = 10a; device grade 3, i cc1 = 100a and i cc2 = 100a. table 18: dc voltage specifications symbol parameter test condition min max units v il input low voltage C C0.5 0.3v cc v v ih input high voltage C 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6ma C 0.4 v v oh output high voltage i ol = C100a v cc C0.2 C v note: 1. all specifications apply to both device grade 6 and device grade 3. micron m25px64 serial flash embedded memory electrical characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac characteristics in the following ac specifications, output high-z is defined as the point where data out is no longer driven; however, this is not applicable to the m25px64 device. table 19: ac measurement conditions symbol parameter min max unit c l load capacitance 30 30 pf input rise and fall times C 5 ns input pulse voltages 0.2v cc 0.8v cc v input timing reference voltages 0.3v cc 0.7v cc v output timing reference voltages v cc / 2 v cc / 2 v figure 31: ac measurement i/o waveform input and output timing reference levels input levels 0.8v cc 0.2v cc 0.7v cc 0.3v cc 0.5v cc table 20: capacitance symbol parameter test condition min max unit notes c in/out input/output capacitance (dq0/dq1) v out = 0 v C 8 pf 1 c in input capacitance (other pins) v in = 0 v C 6 pf note: 1. values are sampled only, not 100% tested, at t a =25c and a frequency of 33mhz. micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 21: ac specifications (75mhz) note 1 applies to the entire table. symbol alt. parameter min typ max unit notes f c f c clock frequency for all commands (except read) d.c. C 75 mhz f r C clock frequency for read command d.c. C 33 mhz t ch t clh clock high time 6 C C ns 2 t cl t cll clock low time 6 C C ns 2 t clch C clock rise time (peak to peak) 0.1 C C v/ns 3, 4 t chcl C clock fall time (peak to peak) 0.1 C C v/ns 3, 4 t slch t css s# active setup time (relative to c) 5 C C ns t chsl s# not active hold time (relative to c) 5 C C ns t dvch t dsu data in setup time 2 C C ns t chdx t dh data in hold time 5 C C ns t chsh C s# active hold time (relative to c) 5 C C ns t shch C s# not active setup time (relative to c) 5 C C ns t shsl t csh s# deselect time 80 C C ns t shqz t dis output disable time C C 8 ns 3 t clqv t v clock low to output valid under 30 pf C C 8 ns clock low to output valid under 10 pf C C 6 ns t clqx t ho output hold time 0 C C ns t hlch C hold# setup time (relative to c) 5 C C ns t chhh C hold# hold time (relative to c) 5 C C ns t hhch C hold# setup time (relative to c) 5 C C ns t chhl C hold# hold time (relative to c) 5 C C ns t hhqx t lz hold# to output low-z C C 8 ns 3 t hlqz t hz hold# to output high-z C C 8 ns 3 t whsl C write protect setup time 20 C C ns 5 t shwl C write protect hold time 100 C C ns 5 t vpphsl C enhanced program supply voltage high (v pph ) to s# low 200 C C ns 6 t dp C s# high to deep power-down mode C C 3 s 3 t rdp C s# high to standby mode C C 30 s 3 t w C write status register cycle time C 1.3 15 ms t pp C page program cycle time (256 bytes) C 0.8 5 ms 7 t pp C page program cycle time (n bytes) C int(n/8) 0.025 5 ms 7, 8 t pp C program otp cycle time (64 bytes) C 0.2 5 ms 7 t sse C subsector erase cycle time C 70 150 ms t se C sector erase cycle time C 0.7 3 s micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 21: ac specifications (75mhz) (continued) note 1 applies to the entire table. symbol alt. parameter min typ max unit notes t be C bulk erase cycle time C 68 160 s notes: 1. ac specification values for 75mhz operations shown here are allowed only on the vcc range 2.7v - 3.6v. typical values are given for t a = 25c. 2. the sum of t ch + t cl signal values must be greater than or equal to 1/f c . 3. the t clch , t chcl , t shqz , t hhqx , t hlqz , t dp , and t rdp signal values are guaranteed by charac- terization, not 100% tested in production. 4. the t clch and t chcl signals clock rise and fall time values are expressed as a slew-rate. 5. the t whsl and t shwl signal values are only applicable as a constraint for a write status register command when srwd bit is set at 1. 6. the t vpphsl signal value for v pph should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. avoid apply- ing v pph to the w/vpp pin during the bulk erase operation. 7. to obtain optimized timings (t pp ) when programming consecutive bytes with the page program command, use one sequence including all the bytes versus several sequences of only a few bytes (1 is less than or equal to n is less than or equal to 256). 8. int(a) corresponds to the upper integer part of a. for example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16. 9. oe# may be delayed by up to t elqv - t glqv after ce#s falling edge without impact to t elqv. micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 32: serial input timing c dq0 s# msb in dq1 tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 33: write protect setup and hold during wrsr when srwd=1 timing c dq0 s# dq1 high impedance w#/v pp twhsl tshwl micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 34: hold timing tchhl thlch thhch thhqx thlqz s# c dq1 dq0 hold# tchhh figure 35: output timing c dq1 s# lsb out dq0 address lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 36: vpph timing s# c dq0 v pp v pph tvpphsl end of command (identified by wip polling) micron m25px64 serial flash embedded memory ac characteristics pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
package information figure 37: vdfpn8 (mlp8, me) 6mm x 8mm 8.00 typ 6.00 typ 4.80 typ 5.16 typ 0.82 min 0.40 0.05 pin 1 id ?0.3 1.27 typ 0.05 max 0.40 +0.08 -0.05 0.85 typ/ 1 max pin 1 id r 0.20 0.05 c 0.10 c m 0.10 c a b 0.15 c a b 0.15 c m 0.05 c (ne - 1) 1.27 typ 8 7 6 5 1 2 3 4 note: 1. drawing is not to scale. micron m25px64 serial flash embedded memory package information pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 38: vdfpn8 (mlp8, md) 6mm x 8mm with reduced d2 dimension 8.00 typ 6.00 typ 4.80 typ 4.70 typ/ 4.725 max 1.05 min 0.40 0.05 pin 1 id ?0.3 1.27 typ 0.05 max 0.40 +0.08 -0.05 0.85 typ/ 1 max pin 1 id r 0.20 0.05 c 0.10 c m 0.10 c a b 0.15 c a b 0.15 c m 0.05 c (ne - 1) 1.27 typ 8 7 6 5 1 2 3 4 note: 1. drawing is not to scale. micron m25px64 serial flash embedded memory package information pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 39: so16w 300 mils body width 16 1 8 9 x 45 1.27 typ 0.10 max 0.40 min/ 1.27 max 0.33 min/ 0.51 max 2.35 min/ 2.65 max 0.23 min/ 0.32 max 0.25 min/ 0.75 max 10.10 min/ 10.50 max 7.40 min/ 7.60 max 10.00 min/ 10.65 max 0.10 min/ 0.30 max 0 min/ 8 max o o note: 1. drawing is not to scale. micron m25px64 serial flash embedded memory package information pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 40: tbga 24-ball, 6mm x 8mm d d solder ball (typ) detail a b ball a1 corner e (4x) (balls down) a top view seating plane c detail a (balls up) 1 bottom view a iso e 2 3 4 5 b c d e e s s c a s b s c index area c c 6.00 +0.10 -0.10 8.00 +0.10 -0.10 2.00 typ 0.20 min 4.00 typ 1.00 typ 1.00 typ 1.00 typ 4.00 typ 1.20 max max max max 0.79 typ 1.50 typ 0.40 +0.05 -0.05 0.15 max 0.15 0.08 0.10 0.10 2.00 typ note: 1. drawing is not to scale. micron m25px64 serial flash embedded memory package information pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device ordering information micron serial nor flash memory is available in different configurations and densities. valid part numbers are at microns part catalog www.micron.com , and feature and specification comparisons are at http://www.micron.com/products . contact your sales representative for devices not found. for more information on how to identify products and top side marking by the process identification letter, refer to technical note, tn-12-24: serial flash memory device marking for the m25p, m25pe, m45pe,m25px, and n25q product families . table 22: part number information scheme part number category category details notes device type m25px = serial flash memory, 4kb and 64kb erasable sectors, dual i/o density 64 = 64mb (8mb x 8-bit) security features C = no extra security 1 so = otp configurable st = otp configurable plus protection at power-up s = cfd programmed with uid operating voltage v = v cc = 2.7 to 3.6v package mp = vdfpn 8mm x 6mm (mlp8) me = vdfpn 8mm x 6mm (mlp8) with reduced d2 dimension mf = so16 (300 mils width) zm = tbga24 6mm x 8mm grade 6 = industrial temperature range: C40c to 85c. device tested with standard test flow (option a is not selected). device tested with high reliability certified test flow, if automotive grade option a is se- lected. 3 = automotive temperature range: C40c to 125c. device tested with high reliability certified test flow. 2 packing e = standard packing t = tape and reel packing lithography b = 110nm, fab 2 diffusion plant blank = 110nm automotive grade a = automotive C40c to 85c (only with device grade 6). device tested with high relia- bility certified test flow. 2 blank = automotive C40c to 125c notes: 1. secure options available upon customer request. 2. micron strongly recommends the use of the automotive grade devices (autograde 6 and grade 3) for use in an automotive environment. the high reliability certified flow (hrcf) is described in the quality note qnee9801. micron m25px64 serial flash embedded memory device ordering information pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
revision history rev. b C 3/2013 ? revised text at the beginning of ordering information. rev. a C 6/2012 ? initial micron release with rebrand. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. micron m25px64 serial flash embedded memory revision history pdf: 09005aef845665ac m25px64.pdf - rev. b 3/13 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.

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